1. Field of the Invention
The present invention relates to a filter circuit for a digital phase-locked loop (PLL) circuit having a digital frequency/phase discriminator which provides two digital signals, and, in particular, to a filter circuit which receives the two digital signals from the digital frequency/phase discriminator and provides a smoothed voltage output for controlling a voltage-controlled oscillator.
2. Description of the Related Art
With regard to the stated practical application, a simple CMOS filter circuit for a phase-locked loop circuit is explained in Deog-Kyoon Jeong, et al., "Design of PLL-Based Clock Generation Circuits," IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 2, April 1987, pp. 255-261. Particular reference is made to FIG. 3b on page 256 of the article, which shows a circuit comprising the series arrangement of the controlled current paths of a p-conducting transistor and an n-conducting transistor. The series arrangement is disposed between the two poles of a source of supply voltage. A square-wave (i.e., digital pulse) signal from a frequency/phase discriminator is fed to one or the other of the two gates serving as the control terminals of the two transistors. The common connecting point between the two transistors is connected via a series RC circuit to one pole of the source of supply voltage. A smooth voltage is taken off this connecting point, across a series resistor. The smoothed voltage is then fed to the control input of the voltage-controlled oscillator (VCO) of the PLL circuit. The two digital signals that control the two transistors are the UP signal and the DOWN signal generated by the frequency/phase discriminator in response to whether the phase of the output of the VCO leads or lags the phase of a reference signal.
The filter circuit as described hereinbefore has, among other disadvantages, the disadvantage that the digital signals are transmitted via parasitic capacitances between the gate and the source/drain of the two transistors to the output. Also, the output voltage (ua) is restricted to the range lying between the magnitude of the control terminal threshold voltage (u.sub.tn) of the n-conducting transistor and the supply voltage (u) as reduced by the magnitude of the control terminal threshold voltage (u.sub.tp): EQU ua=u-.vertline.u.sub.tp .vertline.-.vertline.u.sub.tn .vertline..